Reconfigurable Architectures Workshop
- Preface
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- Invited Talk: Run-Time Reconfiguration at Xilinx
- Steven A. Guccione
- JRoute: A Run-Time Routing API for FPGA Hardware
- Eric Keller
- A Reconfigurable Content Addressable Memory
- Steven A. Guccione; Delon Levi; Daniel Downs
- ATLANTIS - A Hybrid FPGA/RISC Based Reconfigurable System
- O. Brosch; J. Hesser; C. Hinkelbein; K. Kornmesser; T. Kuberka; A. Kugel; R. Männer; H. Singpiel; B. Vettermann
- The Cellular Processor Architecture CEPRA-1X and its Configuration by CDL
- Christian Hochberger; Rolf Hofmann; Klaus-Peter Völkmann; Stefan Waldschmidt
- Loop Pipelining and Optimization for Run Time Reconfiguration
- Kiran Bondalapati; Viktor K. Prasanna
- Compiling Process Algebraic Descriptions into Reconfigurable Logic
- Oliver Diessel; George Milne
- Behavioral Partitioning with Synthesis for MultiFPGA Architectures under Interconnect, Area, and Latency Constraints
- Preetham Lakshmikanthan; Sriram Govindarajan; Vinoo Srinivasan; Ranga Vemuri
- Module Allocation for Dynamically Reconfigurable Systems
- Xuejie Zhang; Kamwing Ng
- Augmenting Modern Superscalar Architectures with Configurable Extended Instructions
- Xianfeng Zhou; Margaret Martonosi
- Complexity Bounds for Lookup Table Implementation of Factored Forms in FPGA Technology Mapping
- Wenyi Feng; Fred J. Meyer; Fabrizio Lombardi
- Optimization of Motion Estimator for Run-Time-Reconfiguration Implementation
- Camel Tanougast; Yves Berviller; Serge Weber
- Constant-Time Hough Transform On A 3D Reconfigurable Mesh Using Fewer Processors
- Yi Pan