Reconfigurable Architectures Workshop


IPDPS 1999 Workshop
Reusable Internal Hardware Templates
Ka-an Agun and Morris Chang

An On-Line Arithmetic-Based Reconfigurable Neuroprocessor
Jean-Luc Beuchat and Eduardo Sanchez

DEFACTO: A Design Environment for Adaptive Computing Technology
Kiran Bondalapati; Pedro Diniz; Phillip Duncan; John Granacki; Mary Hall; Rajeev Jain; and Heidi Ziegler

Domain Specific Mapping for Solving Graph Problems on Reconfigurable Devices
Andreas Dandalis; Alessandro Mei; Victor K. Prasanna

A Web-Based Multiuser Operating System for Reconfigurable Computing
Oliver Diessel; David Kearney; and Grant Wigley

Improved Scaling Simulation of the General Reconfigurable Mesh
Jose Alberto Fernandez-Zepeda; Ramachandran Vaidyanathan; and Jerry L. Trahan

The Re-Configurable Delay-Insensitive FLYSIG Architecture
Wolfram Hardt; Achim Rettberg; and Bernd Kleinjohann

Integrated Block-Processing and Design-Space Exploration in Temporal Partitionning for RTR Architectures
Meenakshi Kaul and Ranga Vemuri

Hardwired-Clusters Partial-Crossbar: A Hierarchical Routing Architecture for Multi-FPGA Systems
Mohammed A.S. Khalid and Jonathan Rose

Digital Signal Processing with General Purpose Microprocessors, DSP and Reconfigurable Logic
Steffen Kohler; Sergej Sawitzki; Achim Gratz; and Rainer G. Spallek

Scalable Hardware-Algorithms for Binary Prefix Sums
R. Lin; K. Nakano; S. Olariu; M.C. Pinotti; J.L. Schwing; and A.Y. Zomaya

MorphoSys: a Reconfigurable Processor Targeted to High Performance Image Application
Guangming Lu; Ming-hau Lee; Hartej Singh; Nader Bagherzadeh; Fadi J. Kurdahi; and Eliseu M. Filho

Bit Summation on the Reconfigurable Mesh
Martin Middendorf

An Efficient Implementation Method of Fractal Image Compression on Dynamically Reconfigurable Architecture
Hidehisa Nagano; Akihiro Matsuura; and Akira Nagoya

Plastic Cell Architecture: A Dynamically Reconfigurable Hardware-based Computer
Hiroshi Nakada; Kiyoshi Oguri; Norbert Imlig; Minoru Inamori; Ryusuke Konishi; Hideyuki Ito; Kouichi Nagami; and Tsunemichi Shiozawa

Leonardo and Discipulus Simplex: An Autonomous, Evolvable Six-Legged Walking Robot
Gilles Ritter; Jean-Michel Puiatti; and Eduardo Sanchez

Interconnect Synthesis for Reconfigurable Multi-FPGA Architectures
Vinoo Srinivasan; Shankar Radhakrishnan; Ranga Vemuri; and Jeff Walrath

Solving Satisfiability Problems on FPGAs using Experimental Unit Propagation Heuristic
Takayuki Suyama; Makoto Yokoo; and Akira Nagoya

FPGA Implementation of Modular Exponentiation
Alexander Tiountchik and Elena Trichina

Configuration Sequencing with Self Configurable Binary Multipliers
Mathew Wojko and Hossam ElGindy