5th Reconfigurable Architectures Workshop

IPDPS 1998 Workshop

Program Committee:

Peter Athanas, Virginia Tech, USA
Don Bouldin, University of Tennessee, USA
Klaus Buchenrieder, Siemens Research, Germany
Steven Casselman, Virtual Computer Corp., USA
Pak Chan, University of California, Santa Cruz, USA
Bernard Courtois, Univ. Grenoble, France
Hossam Elgindy, Univ. of Newcastle, Australia
Rolf Ernst, Univ. Braunschweig, Germany
Masahiro Fujita, Fujitsu Labs., USA
Manfred Glesner, TH Darmstadt, Germany
John Gray, Xilinx Corp., Great Britain
Reiner Hartenstein, Univ. Kaiserslautern, Germany
John McHenry, National Security Agency, USA
Toshiaki Miyazaki, NTT Laboratories, Japan
Brent Nelson, Brigham Young Univ., USA
Viktor Prasanna, Univ. of Southern California, USA
Hartmut Schmeck, Univ. Karlsruhe, Germany
Herman Schmitt, Carnegie Mellon Univ., USA
Michal Servit, Techn. Univ. Prague, Czech Republic
Takayuki Yanagawa, NEC, Tokyo, Japan
Hiroto Yasuura, Kyushu University, Japan


Program:

Dynamic Reconfiguration of a PMMLA (Pipeline of Multiprocessor Modules based on a Linear Array) for High-Throughput Applications
Gautam Ghare, Soo-Young Lee

Virtual FPGAs: Some Steps Behind the Physical Barriers
William Fornaciari, Vincenzo Piuri

A Parallel Algorithm for Minimum Cost Path Computation on Polymorphic Processor Array
P. Baglietto, M. Maresca, M. Migliardi

A Performance Modeling and Analysis Environment for Reconfigurable Computers
Jeffrey Walrath, Ranga Vemuri

Runtime Reconfigurable Routing
Gordon Brebner, Adam Donlin
http://www.dcs.ed.ac.uk/home/gordon/res_custom

An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures
Iyad Ouaiss, Sriram Govindarajan, Vinoo Srinivasan, Meenakshi Kaul, Ranga Vemuri

Temporal Partitioning for Partially-Reconfigurable-Field-Programmable Gate Arrays
J. Spillane, H. Owen

A Java Development and Runtime Environment for Reconfigurable Computing
Don Davis, Michael Barr, Toby Bennett, Stephen Edwards, Jonathan Harris, Ian Miller, Chris Schank
http://www.tsi-telsys.com

Synthesizing Reconfigurable Sequential Machines Using Tabular Model
Kamlesh Rath, Jian Li

Evaluation of a Low-Power Reconfigurable DSP Architecture
Arthur Abnous, Katsunori Seno, Yuji Ichikawa, Marlene Wan, Jan Rabaey

A Reconfigurable Hardware-Monitor for Communication-Analysis in Distributed Real-Time Systems
Andreas Kirschbaum, Juergen Becker, Manfred Glesner
http://www.microelectronic.e-technik.tu-darmstadt.de

On Reconfigurable Co-Processing Units
R. Hartenstein, M. Herz, T. Hoffmann, U. Nageldinger

A Mathematical Benefit Analysis of Context Switching Reconfigurable Computing
S.M. Scalera, J.J. Murray, S. Lease

A Configurable Computing Approach Towards Real-time Target Tracking
B. Pudipeddi, A.L. Abbott, P.M. Athanas

HOSMII: A Virtual Hardware Integrated with DRAM
Yuichiro Shibata, Hidenori Miyazaki, Xiao-ping Ling, Hideharu Amano

Hardware Reconfigurable Neural Networks
Jean-Luc Beuchat, Jacques-Olivier Haenni, Eduardo Sanchez
http://lslwww.epfl.ch/

A Simulator for the Reconfigurable Mesh Architecture
C. Steckel, M. Middendorf, H. ElGindy, H. Schmeck

PACE: Processor Architectures for Circuit Emulation
Reiner Kolla, Oliver Springauf